1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device for storing analog data in a memory cell transistor having a floating gate electrode.
2. Description of the Related Art
An electrically erasable programmable ROM (EEPROM) comprises a number of memory cells, each in turn comprising a single transistor for recording electrically erasable information. Each transistor has a double gate electrode structure including a floating gate electrode and a control gate electrode. Data is written into such a memory cell transistor by applying hot electrons generated on the drain region side of the floating gate electrode into the floating gate electrode with acceleration, and data is read therefrom by detecting a difference in operating characteristics of the transistor between when it is and when it is not in a state where electric charges are stored in its floating gate electrode.
FIG. 1 is a plan view showing the memory cell of a non-volatile semiconductor memory device having a floating gate electrode; FIG. 2 is a cross sectional view of the device along the line X--X in FIG. 1. The memory cell shown in the drawings have a split gate electrode structure in which a control gate electrode is arranged partly overlapping with floating gate electrodes.
On the surface region of a P-type silicon substrate 1, a selectively thick oxide film (LOCOS) is formed. The film constitutes a number of rectangular isolation regions 2 to separate element regions. Floating gate electrodes 4 are formed on the silicon substrate 1 via an oxide film 3, one for each memory cell, bridging adjacent separated regions 2. A further oxide film 5 is formed on each of the floating gate electrodes 4, this film 5 being thick around the center of the gate electrode 4 and resultantly causing cusped edges of the floating gate electrode 4. With cusped edges of the floating gate electrode 4, an electric field tends to be concentrated in the vicinity of the edges in a data erasing operation.
On the silicon substrate 1 carrying a number of floating gate electrodes 4, control gate electrodes 6 are formed one for each row of the floating gate electrodes 4. Each control gate electrode 6 is formed partially overlapping with the floating gate electrodes 4 of the corresponding row, and the rest with the silicon substrate 1 via the oxide film 3. Floating gate electrodes 4 and control gate electrodes 6 are arranged plane symmetrically with respect to respective adjacent ones. Further, N-type first diffusion layers 7 are formed in the substrate region between adjacent control gate electrodes 6, while a second diffusion region 8 is formed in the substrate region between adjacent floating regions 4. First diffusion layers 7 are each discrete from one another, being sandwiched by isolation regions 2 between adjacent control gate electrodes 6. A second diffusion layer 7 continuously extends in the same direction in which the control gate electrode 6 extends. A floating gate electrode 4, a control gate electrode 6, a first diffusion layer 7, and a second diffusion layer 8 together constitute a memory cell transistor.
Above the control gate electrodes 6 via an oxide film 9, aluminum lines 10 are provided intersecting the control gate electrodes 6. Each aluminum line 10 is connected to the first diffusion layer 7, passing through an contact hole 11.
With the above-structured memory cell transistor, a resistance value between the source region and the drain region thereof varies depending on the amount of electric charges applied to the floating gate electrode 4. In other words, when electric charges are applied to floating gate electrode 4, the resistance value of the floating gate electrodes 4 are caused to vary in an analog manner. Due to this variation, a memory cell transistor presents different operation characteristics between when it is and it is not in a state where electric charges are stored therein. As the difference of the operating characteristics differs depending on the amount of applied electric charges, respective differences are set to correspond to respective information to be written into a memory cell transistor.
FIG. 3 is a diagram showing the circuit of a memory cell shown in FIG. 1. In the drawing, memory cells are arranged in four rows and four columns (4.times.4).
A memory cell transistor 20 of a double gate electrode structure has a control gate electrode 6 connected to a word line 21, and first and second diffusion layers 7, 8 respectively connected to a bit line 22 and a source line 23. Bit lines 22 are connected via selection transistors 24 to a data line 25. The data line 25 is in turn connected via a resistor 26 to a read control circuit 27. The bit lines 22 are also connected to sense amplifiers (not shown) each for reading voltage values. On the other hand, source lines 23 are connected to a power line 28. The power line 28 is in turn connected to a write control circuit 29.
In general, a control gate electrode 6 formed common to respective memory cell transistors 20 is used to serve as a word line 21, while an aluminum line 10 connected to the first diffusion layer 7 is used to serve as a source line 22. The first diffusion layer 8 extending in parallel to the control gate electrode 6 is used to serve as a source line 23.
Row selection information LS1 to LS4 are generated based on row address information. Selection of one word line 21 referring to the low selection information LS1 to LS4 will activate a specific row of memory cell transistors 20. Column selection signals CS1 to CS4 are generated based on column address information. Turning on one selection transistor 24 referring to the column selection information CS1 to CS4 will activate a specific column of memory cell transistors 20. With this arrangement, one of a number of memory cell transistors arranged in rows and columns is designated according to row and column address information, and connected to the data line 25.
For writing analog information into a memory cell register 20, application of electric charges (write) and assurance of an applied amount of electric charges (read) are repeatedly conducted in a short cycle in order to improve recording accuracy. That is, data is being written into a memory cell transistor 20 while data is being read therefrom, and a read operation is halted when the content of data just read matches the content of data to be stored.
A write clock .phi.w rises in a constant cycle only for a constant time period, whose pulse height becomes higher as time passes, as shown in FIG. 4. Outputted by the write control circuit 29, a write clock .phi.w passes through the power line 28 and the source line 23, and is supplied to a memory cell transistor 20. At this time, the electric potential of the data line 25 is decreased in synchronism with the write clock .phi.w, becoming as low as the ground potential. As a result, a current flows from the source line 23 via a selected memory cell transistor 20 to the it line 22 during a period when a write clock .phi.w remains risen, hereby electric charges are applied to a floating gate electrode 4.
On the other hand, a read clock .phi.w rises while a write clock .phi.w is not, whose pulse height remains unchanged. Outputted by the read clock circuit 27, a read clock .phi. passes through the resistance 26 and the bit line 20, and is supplied to a selected memory cell transistor 20. At this time, the electric potential of the power line 28 is decreased in synchronism with a read clock .phi.r, becoming as low as the ground potential. As a result, a current flows through the resistance 26, the data line 25, a selected memory cell transistor 20, to the power line 28. The electric potential of the bit line 22 is then varied to take the value in accordance with the ratio between the resistance value of the memory cell transistor 20 and the resistance value of the resistor 26. This potential variation is detected by a sense amplifier connected to the bit line 22 so that write and read operations are repeatedly conducted until the electric potential value just read matches the value corresponding to the information to be written in the memory cell transistor 20.
As described above, in the above memory device, since the result of a read operation is set corresponding to an analog value to be stored (i.e., a write operation is conducted while comparing the data to be written and the data just read), the memory device is unlikely to be affected by the inconsistent characteristics of memory cell transistors 20.
However, the write control circuit 29 which generates a write clock .phi.w with increasing pulse height as time passes requires a high voltage power source and a circuit structure capable of controlling a high voltage. In controlling a high voltage, a switching element having sufficient driving capability and tolerance is generally needed. Thus, such a circuit resultantly has a complicated structure, and tends to be affected by power source noises and cause erroneous judgement of stored information.